The present invention relates to an input/output circuit for an integrated circuit. More specifically, the present invention relates to a controlled impedance for an input/output circuit of an integrated circuit.
Programmable logic devices (PLDs), such as field programmable gate arrays (FPGAs), typically include input/output blocks (IOBs) for providing and receiving external data. An IOB will therefore include an output driver circuit. FIG. 1 is a block diagram of a conventional output driver circuit 100, which includes an input terminal 101, an output terminal 102, p-channel transistors 1031-103N, n-channel transistors 1041-104N and I/O pad 105. Input terminal 101 is coupled to the gates of transistors 1031-103N and to the gates of transistors 1041-104N. The source terminals of p-channel transistors 1031-103N are coupled to a Vcc supply voltage terminal, and the source terminals of n-channel transistors 1041-104N are coupled to a ground terminal. The drain terminals of transistors 1031-103N and 1041-104N are coupled to I/O pad 105 through output terminal 102.
When a logic low signal is applied to input terminal 101, p-channel transistors 1031-103N are all turned on, thereby coupling I/O pad 105 to the Vcc supply voltage terminal. In this condition, driver circuit 100 presents a predetermined resistance to I/O pad 105. This resistance is determined by the on-resistances of transistors 1031-103N, taken in parallel.
Similarly, when a logic high signal is applied to input terminal 101, n-channel transistors 1041-104N are all turned on, thereby coupling I/O pad 105 to the ground terminal. In this condition, driver circuit 100 presents a predetermined resistance to I/O pad 105. This resistance is determined by the on-resistances of transistors 1041-104N, taken in parallel.
In certain circumstances, it is desirable for the resistance presented to I/O pad 105 to have a predetermined relationship with an external resistance coupled to I/O pad 105. For example, it may be desirable for the resistance presented to I/O pad 105 to match an impedance of a trace or wire coupled to I/O pad 105 to improve signal integrity.
Unfortunately, the resistance presented by output driver circuit 100 is fixed at a predetermined value, thereby preventing the driver circuit from being optimized for different trace or wire impedances. Thus, the operating flexibility of driver circuit 100 is limited. In addition, the predetermined resistance value of output driver circuit 100 will vary in response to temperature, voltage and/or process variations. Thus, even if the predetermined resistance of output driver circuit 100 initially has a desirable relationship with a trace or wire impedance coupled to I/O pad 105, this relationship may shift as the resistance of output driver circuit 100 changes in response to changes in temperature, voltage or process.
It would therefore be desirable to have an output driver circuit which overcomes the deficiencies of the above described driver circuit 100.
Accordingly, the present invention provides a system for controlling the impedances of output driver circuits on an integrated circuit chip. At least one output driver circuit is selected to operate as a p-channel reference circuit, and at least one output driver circuit is selected to operate as an n-channel reference circuit. Other output driver circuits are selected to operate as active output driver circuits and/or line termination circuits.
In one embodiment, the p-channel reference circuit includes a first set of p-channel transistors coupled in parallel between a Vcc supply terminal and a first pad, and a p-channel reference resistor RPREF coupled between the first pad and a ground supply terminal. A control circuit determines which subset of transistors in the first set of p-channel transistors should be turned on to provide a pre-determined correspondence with the reference resistor RPREF. For example, the control circuit may determine which subset of transistors in the first set of p-channel transistors should be turned on to match the resistance of reference resistor RPREF. To make this determination, a first reference voltage generator provides a p-channel reference voltage VPREF to a first comparator. The first comparator compares the p-channel reference voltage VPREF with the voltage on the first pad. In response, the first comparator generates a control signal, which indicates whether the resistance of turned on transistors in the first set of p-channel transistors has a determined relationship with respect to the p-channel reference resistor RPREF and the p-channel reference voltage VPREF. The control circuit adjusts the subset of turned on p-channel transistors until the desired correspondence is provided.
The control circuit then addresses a selected group of one or more of the active output driver circuits, and transmits information identifying the determined subset of turned on p-channel transistors. This selected group of active output driver circuits will then turn on transistors corresponding to the determined subset of p-channel transistors to drive a logic high output signal, or provide a desired line termination.
In one embodiment, the control circuit dynamically updates the determined subset of p-channel transistors during operation of the chip, thereby compensating for variations in temperature, voltage and process.
In another embodiment, the first reference voltage generator is configured to provide a plurality of different p-channel reference voltages VPREF. The control circuit then determines different subsets of turned on p-channel transistors for each of the different p-channel reference voltages. The control circuit then addresses different groups of active output driver circuits, with each of the different groups being configured to enable different subsets of p-channel transistors, as determined by the control circuit.
In one embodiment, the first set of p-channel transistors includes fine adjustment p-channel transistors having the same resistance, and coarse adjustment p-channel transistors having binary weighted resistances.
The n-channel reference circuit is configured and controlled in a manner similar to p-channel reference circuit. More specifically, the n-channel reference circuit includes a first set of n-channel transistors coupled in parallel between a ground supply terminal and a second pad, and an n-channel reference resistor REREF coupled between the second pad and the Vcc supply terminal. A control circuit determines which subset of transistors in the first set of n-channel transistors should be turned on to provide a pre-determined correspondence with the reference resistor REREF. To make this determination, a second reference voltage generator provides an n-channel reference voltage VNREF to a second comparator. The second comparator compares the n-channel reference voltage VNREF with the voltage on the second pad. In response, the second comparator generates a control signal, which indicates whether the resistance of turned on transistors in the first set of n-channel transistors has a determined relationship with respect to the n-channel reference resistor RNREF and the n-channel reference voltage VNREF. The control circuit adjusts the subset of turned on n-channel transistors until the desired correspondence is provided.
The control circuit then addresses a selected group of one or more of the active output driver circuits, and transmits information identifying the determined subset of turned on n-channel transistors. This selected group of active output driver circuits will then turn on transistors corresponding to the determined subset of n-channel transistors to drive a logic low output signal, or provide a desired line termination.
In general, the n-channel reference circuit can be controlled in the same manner as the p-channel reference circuit.
In a particular embodiment, the subset of p-channel transistors determined by the p-channel reference circuit is transmitted to the n-channel reference circuit. In response, the n-channel reference circuit turns on a corresponding subset of p-channel transistors to provide the n-channel reference resistance. This eliminates the need for two separate external reference resistors.
The present invention will be more fully understood in view of the following description and drawings.